Supports up to 4 Masters (e.g., application processors or modem ICs) and 16 Slaves (e.g., PMICs or voltage regulators) on a single bus. Speed Classes: Low Speed (LS): 32 kHz to 15 MHz. High Speed (HS): 32 kHz to 26 MHz.
The PDF details:
The SPMI bus consists of two wires:
The MIPI Alliance recently announced that SPMI is being integrated into broader power management frameworks like (I-squared-C, Improved) but remains distinct for low-power, legacy PMICs. Future revisions of the spec (v4.0 expected after 2026) will likely include: mipi spmi specification pdf
Here's a concise post you can use to share information and a link about the MIPI SPMI specification PDF. Supports up to 4 Masters (e
The full is available exclusively to MIPI Alliance members . The PDF details: The SPMI bus consists of
was designed as a two-wire, low-latency, high-speed serial interface specifically for power management. It is a hardware interface plus a command protocol that allows an application processor to read/write registers on multiple PMICs using a single bus.